The present invention relates to semiconductor memories and more particularly to a dynamic type RAM (random access memory). The invention relates to significantly effective technology to be utilized in such a RAM which adopts half precharge system and which has a memory mat select function.
A memory cell of one bit in a dynamic type RAM comprises an information storage capacitor Cs and an address selecting MOSFET Qm, and information of logic "1", "0" is stored in the memory cell in the form of whether charge exists or not in the capacitor C.sub.s. The information is read in that the MOSFET Qm is turned on and the capacitor C.sub.s is connected to a data line D whereby it is sensed what variation of potential occurs in the data line D corresponding to the charge quantity stored in the capacitor C.sub.s. In the abovementioned capacitor C.sub.s, MOS capacitance between a gate electrode and a channel is utilized. Consequently, the gate electrode of the capacitor Cs is supplied with the power source voltage stably. Alternatively, according to the ion implantation method, a channel region is formed on a semiconductor surface under the gate electrode of the capacitor C.sub.s. As a system of forming the read reference voltage of the memory cell, the so-called half precharge system (or dummy cellless system) which makes precharge of the data line a half level, is disclosed in ISSCC84, DIGEST OF TECHNICAL PAPERS, p276.about.p277 and in "NIKKEI ELECTRONICS", Feb. 11, 1985, p243.about.p263, published by NIKKEI McGRAW-HILL.
Half precharge of complementary data lines can be formed in that high level in one data line among the complementary data lines amplified by a sense amplifier and low level in the other data line are short-circuited electrically. In this case, a number of complementary data line pairs are provided with short-circuit MOSFETs respectively. Consequently, gates of the number of short-circuit (precharge) MOSFETs are connected commonly to the precharge signal line. Thereby, a relatively large load (parasitic) capacitance is coupled with the precharge signal line. Also a memory array is constituted by a plurality of memory mats, and a specific mat assigned in address among them is set to a selective state whereby the consumption power can be made low. In this case, after the inputted address signal is established within the dynamic type RAM, a precharge control signal of the memory mat to be selected must be drawn from high level into low level. However, the drawing speed becomes slow because the load capacitance of the precharge signal line is made relatively large. Since the selection timing of the word line must be delayed corresponding to the drawing speed, the operation speed of the dynamic type RAM becomes slow.
A dynamic type RAMs of a shared sense system type is disclosed in IEEE JOURNAL OF SOLID-STATE CORCUITS, vol. SC-77, No. 5 (October, 1972), p336.about..about.p340. In the dynamic type RAM of such a shared sense system, a sense amplifier is arranged at an intermediate portion of complementary data lines, and memory mats are formed on both sides of the sense amplifier. Selection of the memory mats is performed by complementary switch control of the sharing switches such as are constituted by MOSFETs installed in the complementary data lines on both sides of the sense amplifier.
If the storage capacitance of the memory cell is made C.sub.s, the parasitic capacitance coupled with the complementary data lines is made C.sub.b, and the write voltage is made V.sub.s, the signal amount read from the complementary data memory cell into the complementary data lines becomes smaller as the parasitic capacitance of the complementary data lines becomes larger as given by following formula. In the following formula, ".alpha." is a constant determined by reading system. EQU Vsig=V.sub.s .times..alpha..times.C.sub.s /(C.sub.s +C.sub.b)
In order to increase the signal amount read from the memory cell into the complementary data lines by a drive operation of the word line to selective level in the selecting operation of the memory cell, in the dynamic type RAM of a shared sense system, the complementary data lines are made non-conductive electrically with each other on both sides of the sense amplifier when a prescribed word line at least is driven to the selective level.
Consequently, in the dynamic type RAM of a shared sense system in the prior art, sharing switches on both sides are initialized to the ON-state in the chip non-selective state, and the sharing switch at a non-selected mat side is turned off based on the address signal supplied from outside in the chip selective state. After the OFF-state of the sharing switch is established, the selective drive of the word line is carried out.